This subject opens up the processor that Computer Organization treated as a black box. The classic course uses the Intel 8086, a 16-bit processor from 1978, as its teaching model, because it shows every idea clearly: registers, buses, addressing, interrupts, and how to connect memory and devices. The same ideas still run in every CPU, from your laptop’s x86 to the microcontroller in a smart sensor. This article revisits the five units of the JNTUK course.
Unit 1: The 8086 architecture
Registers and buses
The 8086 has a 16-bit data bus, a 20-bit address bus (so it can address 2²⁰ = 1 MB) and a clock of 5 to 10 MHz in the original parts.
| Register group | Registers | Role |
|---|---|---|
| General purpose | AX, BX, CX, DX (each split into high and low bytes, such as AH and AL) | Data and arithmetic; CX is the loop counter, DX holds I/O ports |
| Pointer and index | SP, BP, SI, DI | Stack pointer, base pointer, string source and destination |
| Segment | CS, DS, SS, ES | Code, data, stack and extra segments |
| Instruction pointer | IP | Offset of the next instruction |
| Flags | 16-bit flag register | Carry, zero, sign, overflow, parity, auxiliary carry, and control flags (trap, interrupt, direction) |
Segmented memory
Memory is divided into segments of up to 64 KB. A physical address is built from a segment and an offset:
Physical address = segment × 16 + offset
For example, segment 2000H and offset 0050H give 20050H. This was a way to reach 1 MB with 16-bit registers.
Internal organization
The 8086 has two units that work in parallel, which is an early form of pipelining:
| Unit | Job |
|---|---|
| Bus Interface Unit (BIU) | Fetches instructions into a 6-byte queue, calculates addresses, reads and writes memory |
| Execution Unit (EU) | Decodes and executes instructions from the queue |
The processor has minimum mode (single processor, generates its own control signals) and maximum mode (multiprocessor systems using a bus controller, the 8288).
Today: every x86 PC still boots in this 16-bit “real mode” for a moment before the firmware switches to 32-bit or 64-bit mode. The instruction queue is the ancestor of the deep pipelines and prefetching in modern CPUs.
Unit 2: Instruction set and assembly programming
Addressing modes
| Mode | Example | The operand is |
|---|---|---|
| Immediate | MOV AX, 1234H |
In the instruction |
| Register | MOV AX, BX |
In a register |
| Direct | MOV AX, [2000H] |
At a memory address in the instruction |
| Register indirect | MOV AX, [BX] |
At the address held in a register |
| Based / indexed | MOV AX, [BX+SI] |
At the sum of registers |
| Based indexed with displacement | MOV AX, [BX+SI+10H] |
At registers plus a constant |
Instruction groups
| Group | Examples |
|---|---|
| Data transfer | MOV, PUSH, POP, XCHG, LEA, IN, OUT |
| Arithmetic | ADD, ADC, SUB, MUL, DIV, INC, DEC, CMP |
| Logical and shift | AND, OR, XOR, NOT, SHL, SHR, ROL, ROR |
| Branching | JMP, JZ, JNZ, JC, CALL, RET, LOOP |
| String | MOVS, CMPS, SCAS, LODS, STOS with the REP prefix |
| Processor control | CLC, STC, CLI, STI, HLT |
Writing assembly
An assembly program uses assembler directives such as SEGMENT, ENDS, ASSUME, DB, DW and END. A tiny example that adds two numbers:
MOV AL, 05H then ADD AL, 03H leaves 08H in AL.
Typical exercises: add or multiply multi-byte numbers, find the largest value in an array, sort an array, count ones in a byte, and string operations such as copying or reversing. Procedures (CALL/RET) use the stack, a last-in first-out region addressed by SS:SP; macros insert code at assembly time.
Today: the instruction groups are the same ones in every ISA, including ARM and RISC-V. When you read a stack trace, a disassembly in
gdbor a compiler’s output, you are reading this kind of code, andMOV,ADD,JMP,CALLandRETlook the same.
Unit 3: Memory and I/O interfacing, and interrupts
Memory interfacing
To connect memory chips, you must decode the address bus so each chip responds to its own range.
| Concept | Meaning |
|---|---|
| Address decoding | Higher address lines go through a decoder (such as the 74138 3-to-8) to produce chip-select signals |
| Memory banks | The 8086 splits 1 MB into an even bank (data lines D0 to D7) and an odd bank (D8 to D15), chosen by A0 and BHE |
| Wait states | Extra clock cycles inserted when memory is slower than the processor |
Chip size: a memory with n address lines holds 2ⁿ locations. To build 8 KB from 2 KB chips needs four chips and a 2-to-4 decoder.
I/O interfacing
| Method | Description |
|---|---|
| Memory-mapped I/O | Devices share the memory address space; ordinary memory instructions are used |
| Isolated (port-mapped) I/O | Separate I/O address space (64 K ports), used with IN and OUT |
Data transfer methods are polling (the CPU repeatedly checks a status flag), interrupts (the device signals the CPU) and DMA (a controller moves data directly between memory and device).
Interrupts
An interrupt pauses the program to run an interrupt service routine (ISR). The 8086 has 256 interrupt types, with their addresses stored in the interrupt vector table in the first 1 KB of memory (4 bytes per vector).
| Type | Examples |
|---|---|
| Hardware, non-maskable | NMI: cannot be disabled |
| Hardware, maskable | INTR: can be disabled with CLI |
| Software | INT n instruction (for example INT 21H for DOS services) |
| Exceptions | Divide error, single-step, overflow |
Today: interrupts are how your keyboard, network card and disk talk to the CPU. In Linux,
/proc/interruptsshows the counts, and high interrupt load or a mis-balanced interrupt can be a real performance problem. The same memory-mapped I/O approach is how drivers talk to hardware, and DMA is how network cards and NVMe drives move data without using the CPU.
Unit 4: Support chips and peripheral interfacing
Because early processors had few pins, separate chips added functions.
| Chip | Function |
|---|---|
| 8255 PPI (programmable peripheral interface) | 24 I/O lines in ports A, B, C; modes 0 (simple I/O), 1 (strobed) and 2 (bidirectional); drives switches, LEDs, keyboards, displays |
| 8253/8254 timer | Three 16-bit counters for delays, square waves and pulse counting |
| 8259 PIC (interrupt controller) | Handles up to 8 interrupt lines (cascadable to 64) with priorities |
| 8237 DMA controller | Four DMA channels |
| 8251 USART | Serial communication, synchronous and asynchronous |
| Latch (8282) and transceiver (8286) | Hold the address and buffer the data bus |
Interfacing examples
- Keyboard matrix: rows and columns are scanned to find which key is pressed.
- 7-segment display and LCD: the processor writes the code for each digit or character.
- ADC and DAC: an analog-to-digital converter (0808/0809) reads sensors; a digital-to-analog converter (0800) produces analog output such as waveforms.
- Stepper motor: driven by a pattern of pulses that energize its coils in sequence.
- Serial communication: RS-232 and the idea of baud rate, start and stop bits, and parity.
Today: these functions are inside the chipset of every PC, or inside a single SoC. Timers, interrupt controllers and UARTs are the same blocks you configure on a Raspberry Pi or an ESP32, and the ADC is how any sensor reaches a digital system.
Unit 5: The 8051 microcontroller
A microcontroller puts a CPU, memory and I/O on a single chip; the classic one is the Intel 8051, which is still used in teaching.
| Feature | Detail |
|---|---|
| CPU | 8-bit |
| ROM (program) | 4 KB on-chip |
| RAM (data) | 128 bytes on-chip, including 4 register banks and bit-addressable area |
| I/O | 4 ports (P0 to P3), 32 pins |
| Timers/counters | Two 16-bit (Timer 0 and Timer 1) |
| Serial port | One full-duplex UART |
| Interrupts | Five sources: two external, two timer, one serial |
Key differences from the 8086:
| Point | Microprocessor (8086) | Microcontroller (8051) |
|---|---|---|
| Memory and I/O | External chips needed | On the chip |
| Cost and size | Higher | Low |
| Typical use | General-purpose computing | Embedded control: appliances, toys, sensors |
| Instruction style | Many instructions, memory-heavy | Bit-level control, fast I/O |
The 8051 has special instructions for single bit operations (SETB, CLR, JB) and a special function register (SFR) area for control. Typical programs: blink an LED on a port, generate a delay with a timer, send a character through the serial port, and read a switch.
Today: modern microcontrollers such as AVR (Arduino), ARM Cortex-M (STM32), ESP32 and the RP2040 (Raspberry Pi Pico) follow the same design. Every IoT sensor, smart meter, drone controller and car ECU contains one. The server you manage also has a small microcontroller on its motherboard, the baseboard management controller (BMC), that allows remote power control.
One-minute recap
| Unit | Key idea | You meet it in |
|---|---|---|
| 1. 8086 architecture | Registers, segment × 16 + offset, BIU and EU | CPU boot, pipelining ideas |
| 2. Instruction set | Addressing modes, instruction groups, stack | Disassembly, debuggers, compilers |
| 3. Memory, I/O and interrupts | Address decoding, memory-mapped vs isolated I/O, vector table | Device drivers, /proc/interrupts, DMA |
| 4. Support chips | 8255, 8254, 8259, 8237, 8251 | Chipsets, UARTs and timers on SoCs |
| 5. 8051 | CPU, memory, ports, timers and UART on one chip | Arduino, ESP32, IoT devices, server BMCs |
Next in Engineering Revisited: OOPS through Java.
Written by Claude, Anthropic’s AI assistant, as part of Engineering Revisited, a quick refresher of the B.Tech subjects one at a time.